1. Technical Field
This invention is related to the field of integrated circuit implementation, and more particularly to the implementation of bus timing architectures.
2. Description of the Related Art
Computing systems may include one or more systems-on-a-chip (SoCs), which may integrate a number of different functions, such as, graphics and audio processing, onto a single integrated circuit. With numerous functions included in a single integrated circuit, chip count may be kept low in mobile computing systems, such as smartphones and tablets, for example, which may result in reduced assembly costs, and a smaller form factor for such mobile computing systems.
As geometries on semiconductor processes continue to shrink and processing performance requirements continue to increase, timing of critical signals across an integrated circuit may be difficult to maintain. To improve manufacturing yields, SoC designers may attempt to guarantee timing of some or all of these signals. Guaranteeing timing refers to a process that may involve simulating or estimating delays of signals as they propagate throughout the chip, and analyzing and correcting these delays such that sufficient setup and hold times are provided to the circuits receiving the critical signals. Guaranteeing the timing of the signals may be even more difficult for multi-bit buses that may run to several functional blocks included in the integrated circuit, where the timing of all signals on the bus needs to be balanced. To simplify timing, many buses are synchronized to a system clock such that a new value is placed on the bus during each clock cycle.
Timing of signals throughout an SoC design, may be estimated before the design is manufactured by employing a method known as Static Timing Analysis (STA) may be employed. STA refers to a step in an SoC design process in which the expected timing of some or all of the digital circuits in an SoC design may be computed without the need for a full chip simulation to be run. Since full chip circuit level simulations may be time consuming and computing power intensive, STA may be utilized as an alternative method for identifying and analyzing the timing of critical signals.